The subject invention is directed generally to frequency synthesizers, and more particularly to an improved variable frequency synthesizer that utilizes a modulo N counter, where N is a product of prime numbers, for achieving reduced spurious outputs and fast switching speeds.
Variable frequency synthesizers are utilized in applications such as radar and communications, and generally provide an output signal whose frequency is controlled by a digital input. A known variable frequency synthesizer includes a modulo 2i counter and an inversion network to generate a digital triangular staircase signal. A digital-to-analog converter converts the triangular signal to an analog signal which is then low pass filtered. The low pass filter output is hard limited to produce a square wave whose average frequency is the desired output frequency. The square wave is provided as a reference frequency to a phase locked loop which upconverts the reference frequency to a higher frequency, for example.
A consideration with the foregoing variable frequency synthesizer is the production of spurious signals near the desired output frequency. These spurious signals are generated in the digital portion of the frequency synthesizer and are inherent in present state of the art designs. This problem is particularly acute when the frequency step size is very small relative to the tuning bandwidth and the time to switch from one frequency to another is very short. The spurious signals place limitations on the performance of the radar or communications system, for example, that includes the frequency synthesizer.